Reset PXI_Clk10 Counters on PXI_Trig

Data
Type
Access Applies to Coercion High-Level VIs
Boolean Data R/W N/A None None

Description

Specifies or returns whether or not PXI_Clk10 clock dividers should reset when the device receives an update pulse on a PXI_Trig line. You can specify which PXI_Trig line contains the update pulse using the Reset Synchronization Clock PXI_Trig Line property. If TRUE, the PXI_Clk10 dividers reset on the rising edge of the update pulse.

Note Note  
  • This property is supported only on signal-based devices.
  • This property is unsupported by the PXIe-6674T.

Property Node Path

niSync»Synchronization Clock Properties»Reset PXI_Clk10 Counters on PXI_Trig