Reset PFI0 Counters on PXI_Trig

Data
Type
Access Applies to Coercion High-Level VIs
Boolean Value R/W N/A None None

Description

Specifies or returns whether or not the PFI0 clock dividers should reset when the device receives an update pulse on a PXI_Trig line. You can specify which PXI_Trig line contains the update pulse using the Reset Synchronization Clock PXI_Trig Line parameter of the niSync Property Node. If TRUE, the PFI0 dividers reset on the rising edge of the update pulse.

Note Note  
  • This property is supported only on signal-based devices.
  • This property is not supported by the PXIe-6674T

Property Node Path

niSync»Synchronization Clock Properties»Reset PFI0 Counters on PXI_Trig