Enabling and Configuring a Phase-Locked Loop
Complete the following steps to use an NI-Sync device's PLL circuit to phase lock the oscillator of the system timing module to an external clock:
- Connect an external clock to the ClkIn connector on the front panel of the module in the system timing slot of the chassis.
- Place niSync Initialize and select the module in the chassis' system timing slot for resource name.
- Place an niSync Property Node.
- Select Clk Properties»Use PLL? for the first parameter of the niSync Property Node and set its value to TRUE.
- Add another parameter to the niSync Property Node and select Clk Properties»PLL Frequency for the second parameter.
- Right click the PLL Frequency parameter and select Change to Write.
- Wire a control or constant to the PLL Frequency parameter and enter the frequency of the external clock connected to ClkIn. Refer to the device's hardware manual for the reference frequency range supported by the device's PLL circuit.
After completing the preceding steps, the oscillator of the NI-Sync device is configured to enable a phase-locked loop. However, you must create a route from ClkIn to PXI_CLK10_In before you can successfully phase-lock the oscillator to an external clock.
Refer to Routing and Locking to the PLL Reference Clock to complete the phase-locked loop.