Setting and Dividing a Synchronization Clock

Complete the following steps to set and divide the synchronization clock of the front and rear zones of a PXI or PXIe chassis:

  1. Place niSync Initialize.
  2. Place niSync Property Node and select Synchronization Clock Properties»Synchronization Clock Source (PFI, PFI_LVDS) as the first parameter.
  3. Right-click the Synchronization Clock Source (PFI, PFI_LVDS) parameter and select Change To Write.
  4. Wire a control or constant to the Synchronization Clock Source (PFI, PFI_LVDS) parameter. The value you select here becomes the synchronization clock for the front zone of your PXI chassis, which comprises the front panel inputs and outputs of each module. The default is PXI_Clk10.
  5. Add another parameter to the niSync Property Node and select Synchronization Clock Properties»Synchronization Clock Source (PXI_Trig, PXI_Star, PXIe_DStarB).
  6. Wire a control or constant to the Synchronization Clock Source (PXI_Trig, PXI_Star, PXIe_DStarB) parameter. The value you select here becomes the synchronization clock for the back zone of your PXI chassis, which includes all the chassis' backplane trigger lines. The default is PXI_Clk10.
  7. Add another parameter to the niSync Property Node and select Synchronization Clock Properties»Clock Divisor 1 as the third parameter.
    Note Note  Clock Divisor parameters apply to whatever synchronization clock source is placed in the same niSync Property Node. This example sets a clock divisor for both the front and rear zone synchronization clocks, but if the niSync Property Node only contained Synchronization Clock Source (PFI, PFI_LVDS), the Clock Divisor parameters would only divide the synchronization clock for the front zone.
  8. (Optional) Add a fourth parameter to the niSync Property Node and select Synchronization Clock Properties»Clock Divisor 2 to use a second value to divide the synchronization clock.
  9. Wire a control or a constant to the Clock Divisor 1 and/or Clock Divisor 2 parameters and set the number(s) you would like to divide the clock by.
    Note Note  Values for the Clock Divisor 1 and Clock Divisor 2 parameters must be a power of 2, up to 512.

When you complete the preceding steps, you have successfully set the synchronization clock source for both the front and rear zones of the chassis. You have also created two divided synchronization clocks using the values you set for the Clock Divisor 1 and Clock Divisor 2 parameters.