Routing and Locking to the PLL Reference Clock
Prerequisites: Enabling and Configuring a Phase-Locked Loop
After you phase lock the oscillator of the system timing module to an external clock connected to ClkIn, complete the following steps to route the external reference clock from ClkIn to the PXI_Clk10_In connector and wait until the system is phase-locked:
- Place niSync Connect Clock Terminals.
- Select ClkIn as the source and select PXI_Clk10_In as the destination.
- Place a While Loop. Adding a While Loop ensures that the system is phase locked before moving on.
- Place an niSync Property Node inside the While Loop.
- Select Clk Properties»PLL Locked? as the first parameter of the niSync Property Node.
- Wire PLL Locked? to the conditional terminal of the While Loop to stop the loop once the system is phase locked.
- (Optional) Wire an indicator to the PLL Locked? parameter to display PLL lock status on the front panel.
- (Optional) Add a Wait function inside the While Loop to delay iterations of the loop. This eases the load on your processor.
- Place niSync Disconnect Clock Terminals outside the While Loop and wire source and destination to close the clock route between ClkIn and PXI_Clk10_In.
- Place niSync Close to terminate the NI-Sync session.
This program disconnects the clock at ClkIn right after the PLL circuit is locked. To maintain the phase lock throughout a program, place your code outside the While Loop and before niSync Disconnect Clock Terminals. You can now use the phase-locked backplane clock to synchronize modules within the chassis or export it for multi-chassis synchronization.