NISYNC_ATTR_SYNC_CLK_RST_CLK10_CNTR_ON_PXITRIG

Specific Attribute

Data
Type
Access Applies to Coercion High-Level Functions
ViBoolean R/W N/A None None

Description

Specifies or returns whether or not PXI_Clk10 clock dividers should reset when the device receives an update pulse on a PXI_Trig line. You can specify which PXI_Trig line contains the update pulse using the NISYNC_ATTR_SYNC_CLK_RST_PXITRIG_NUM attribute. If TRUE, the PXI_Clk10 dividers reset on the rising edge of the update pulse.

Note Note  
  • This attribute is supported only on signal-based devices.
  • This attribute is unsupported by the PXIe-6674T.