niSync_ConnectSWTrigToTerminal

C Function Prototype

ViStatus niSync_ConnectSWTrigToTerminal (ViSession vi, ViConstString sourceTerminal, ViConstString destinationTerminal, ViConstString synchronizationClock, ViInt32 invert, ViInt32 updateEdge, ViReal64 delay);

Purpose

Connects the global software trigger terminal to a destination trigger terminal.

Once you connect the global software trigger, you can fire the trigger using niSync_SendSoftwareTrigger.

Note Note  The destination terminal you specify in this function determines the full-speed synchronization clock used by the global software trigger. PFI and PFI_LVDS lines are in the front trigger zone, and PXI_Trig, PXI_Star, and PXIe_DStarB lines are in the rear trigger zone.

Parameters

Name Type Description
vi ViSession The session handle that you obtain from niSync_init. The handle identifies a particular instrument session.

sourceTerminal ViConstString Specifies the source software trigger terminal to connect to the destination terminal.

Valid Values:
NISYNC_VAL_SWTRIG_GLOBAL (Default Value)

destinationTerminal ViConstString Specifies the destination trigger terminal that the global software trigger terminal will connect to.

Valid Values:
NISYNC_VAL_PXITRIG0 (Default Value)
NISYNC_VAL_PXITRIG1
NISYNC_VAL_PXITRIG2
NISYNC_VAL_PXITRIG3
NISYNC_VAL_PXITRIG4
NISYNC_VAL_PXITRIG5
NISYNC_VAL_PXITRIG6
NISYNC_VAL_PXITRIG7
NISYNC_VAL_PXISTAR0
NISYNC_VAL_PXISTAR1
NISYNC_VAL_PXISTAR2
NISYNC_VAL_PXISTAR3
NISYNC_VAL_PXISTAR4
NISYNC_VAL_PXISTAR5
NISYNC_VAL_PXISTAR6
NISYNC_VAL_PXISTAR7
NISYNC_VAL_PXISTAR8
NISYNC_VAL_PXISTAR9
NISYNC_VAL_PXISTAR10
NISYNC_VAL_PXISTAR11
NISYNC_VAL_PXISTAR12
NISYNC_VAL_PXISTAR13
NISYNC_VAL_PXISTAR14
NISYNC_VAL_PXISTAR15
NISYNC_VAL_PXISTAR16
NISYNC_VAL_PFI0
NISYNC_VAL_PFI1
NISYNC_VAL_PFI2
NISYNC_VAL_PFI3
NISYNC_VAL_PFI4
NISYNC_VAL_PFI5
NISYNC_VAL_PFILVDS0
NISYNC_VAL_PFILVDS1
NISYNC_VAL_PFILVDS2
NISYNC_VAL_PXIEDSTARB0
NISYNC_VAL_PXIEDSTARB1
NISYNC_VAL_PXIEDSTARB2
NISYNC_VAL_PXIEDSTARB3
NISYNC_VAL_PXIEDSTARB4
NISYNC_VAL_PXIEDSTARB5
NISYNC_VAL_PXIEDSTARB6
NISYNC_VAL_PXIEDSTARB7
NISYNC_VAL_PXIEDSTARB8
NISYNC_VAL_PXIEDSTARB9
NISYNC_VAL_PXIEDSTARB10
NISYNC_VAL_PXIEDSTARB11
NISYNC_VAL_PXIEDSTARB12
NISYNC_VAL_PXIEDSTARB13
NISYNC_VAL_PXIEDSTARB14
NISYNC_VAL_PXIEDSTARB15
NISYNC_VAL_PXIEDSTARB16

Note  Each PXI_Star and PXIe_DStarB trigger is mapped to a single slot. This mapping is vendor specific. Your chassis documentation may describe this mapping in addition to the chassis.ini and pxisys.ini system description files the PXI Specification requires.


synchronizationClock ViConstString Specifies whether to use the full-speed or a divided synchronization clock to control when the global software trigger fires. The global software trigger will be synchronized with the rising or falling edge of the clock you select in this terminal.

Note  
  • Asynchronous connections are not valid for software trigger terminal connections.
  • The source of the synchronization clock for software trigger connections is determined by the destination terminal trigger "zone" ("front" for the PFI and PFI_LVDS lines, and "rear" for the PXI_Trig, PXI_Star, and PXIe_DStarB terminals). The source of the synchronization clock for a given trigger zone can be selected using the NISYNC_ATTR_FRONT_SYNC_CLK_SRC (PFI zone) and NISYNC_ATTR_REAR_SYNC_CLK_SRC (PXI backplane zone) attributes.


Valid Values:
NISYNC_VAL_SYNC_CLK_FULLSPEED (Default Value)
NISYNC_VAL_SYNC_CLK_DIV1
NISYNC_VAL_SYNC_CLK_DIV2
invert ViInt32 Specifies whether or not to invert the digital signal of the Global Software Trigger when it reaches the destination terminal.

Valid Values:
NISYNC_VAL_DONT_INVERT
NISYNC_VAL_INVERT

updateEdge ViInt32 Specifies the synchronization clock update edge that the global software trigger should be propagated on.

Valid Values:
NISYNC_VAL_UPDATE_EDGE_RISING (Default Value)
NISYNC_VAL_UPDATE_EDGE_FALLING

delay ViReal64 Specifies the number of seconds to delay the global software trigger pulse. The delay must be a multiple of the synchronization clock period. The global software trigger can be delayed up to 15 clock cycles for each route.

Default Value: 0.00 seconds

Note Note  This input is not supported on the PXIe-6674.

Return Values