NISYNC_ATTR_SYNC_CLK_RST_DDS_CNTR_ON_PXITRIG

Data
Type
Access Applies to Coercion High-Level Functions
ViBoolean R/W N/A None None

Description

Specifies whether or not the DDS clock dividers should reset when the device receives an update pulse on the PXI_Trig line specified in the NISYNC_ATTR_SYNC_CLK_RST_PXITRIG_NUM attribute. If TRUE, the DDS clock dividers reset on the rising edge of the update pulse.

Note Note  
  • This attribute is supported only on signal-based devices.
  • This attribute is unsupported on the PXIe-6674T.