Data Type |
Access | Applies to | Coercion | High-Level Functions |
---|---|---|---|---|
ViReal64 | R/W | N/A | None | None |
Specifies or returns the phase voltage between an external clock and PXI_Clk10 when you are using the PLL circuit to lock PXI_CLK10 to an external reference clock. You can minimize the time between rising edges of PXI_CLK10 and the external reference clock using this parameter.